1. Field of the Invention
The present invention relates to the reduction of crosstalk in an electronic circuit device or system such as semiconductor integrated circuit (LSI), circuit mounted in a package, and an electronic circuit device mounted on a printed circuit board. In particular, the present invention relates to the application in electronic logic circuit system such as general-purpose processor, signal processor, ASIC, gate array, FPGA, image processor, semiconductor memory, system module, memory module, computer system, portable device system, etc.
2. Description of the Related Art
In the past, a logic circuit has been manufactured as follows: A large or a small circuit having a certain logic functions and called a cell or a block is disposed in a package or on a semiconductor integrated circuit chip or on a printed circuit board. Then, input/output terminals of each cell or circuit block are connected using metal wires. If the semiconductor integrated circuit chip (the components such as ASIC, gate array, FPGA, etc.), package module, or system on substrate can be fabricated within small area, it would be advantageous from economical viewpoint. Therefore, it is desirable that integration density or mounting density of cells, blocks and wires can be made as high as possible.
For this reason, in the field of semiconductor integrated circuit, fabrication technique has been increasingly miniaturized. The mounting technique in package or on substrate has been turned to higher density. However, when it is tried to accommodate a great number of elements and wires within a small region, various problems arise. One of these problems is the problem of crosstalk.
Crosstalk means interference of signals, which may occur between wires when a plurality of wires are arranged at positions physically closer to each other. In general, the functions to be processed by circuit are designed in such manner that the processing can be completed within a given delay time and integrated circuit and system can be operated at a desired frequency. In this case, if design is performed without taking the crosstalk into account, the change of delay time caused under the influence of signal interference is often overlooked. Under such circumstances, semiconductor integrated circuit chip or system may not be operated at the desired frequency.
If semiconductor integrated circuit chip or system is not operated at the desired frequency, the chip or the system must be re-designed, and this means a great loss of cost and time. To avoid such situation, it is necessary to avoid or reduce the problem of delay time degradation due to crosstalk after accurately analyzing degradation of delay time due to crosstalk.
The difficulty in the problem of delay time degradation due to crosstalk is the fact that its influence changes depending on signal arrival time. This is described in the article presented by the present inventors: xe2x80x9cCrosstalk Delay Analysis using Relative Window Methodxe2x80x9d; Proceedings of IEEE International ASIC/SOC Conference 1999, pp. 9-13 (hereinafter referred as the reference 1).
Specifically, delay time is subject to diverse changes (degradation) depending upon the timing of signal arrival time (victim signal arrival time; VSAT) on the wire, for which analysis of delay time is to be performed (hereinafter referred as xe2x80x9cthe wire in questionxe2x80x9d or xe2x80x9cvictimxe2x80x9d) and signal arrival time (aggressor signal arrival time; ASAT) on the wire, which interferes the above wire (hereinafter referred as xe2x80x9cthe adjacent wirexe2x80x9d or xe2x80x9caggressorxe2x80x9d) (Hereinafter, the value of this change is referred as xe2x80x9cdelay time degradation valuexe2x80x9d). FIG. 1 is used to explain an example of delay degradation, which depends upon a combination of signal arrival time of victim and aggressor. A circuit diagram is shown on left side, and a delay degradation characteristic table corresponding to the circuit is given on right side.
In the cited reference 1, relative signal arrival time (RSAT), which is obtained by relatively measuring ASAT using VSAT as a reference, is used to address this problem. In this case, as in FIG. 2, which shows the change of delay degradation value due to relative signal arrival time (RSAT), the delay time degradation values are represented on a graph or a table with the relative signal arrival time on axis of abscissa. This is prepared in advance for a combination of drivers, which drive victim and aggressor. For each actual case, this graph or the table is drawn, and delay time degradation values are calculated.
Further, another difficulty relating to this problem lies in that VSAT or ASAT themselves may change according to the input patterns. FIG. 3 shows this fact. An example of circuit diagram is shown on left side, and a characteristic table is given on right side based on the measurement of the changes of signal arrival time depending on the input patterns (signal paths) to correspond to the circuit. For instance, in case there is a change in a given input pattern, signal is transmitted from in1 to n2 via n1. In this case, the signal arrival time at the node n2 is 0.40 ns. However, in another input pattern change, signal is transmitted from in3 to n2, and signal arrival time at the node n2 is 0.10 ns, and this is different from the above value. For this reason, it is not possible to uniquely determine RSAT, and the degradation table of FIG. 2 cannot be applied in simple manner.
In the reference 1, this problem is addressed by utilizing a concept called xe2x80x9crelative windowxe2x80x9d. FIGS. 4A to 4C show this method. VSAT and ASAT are changed according to the input pattern, and these cannot be obtained as a time at a certain node. Therefore, VSAT or ASAT is calculated as a window with a certain width (FIG. 4A: VSAT and ASAT window calculation). Next, RSAT cannot be uniquely determined, and it is calculated as a window having a width (hereinafter referred as xe2x80x9crelative windowxe2x80x9d) (FIG. 4B: relative window calculation). Here, the relative window is a range from the time when RSAT is at minimum to the time when it is at maximum. The time when RSAT is at minimum is the time when ASAT is at minimum and VSAT is at maximum. On the other hand, the time when RSAT is at maximum is the time when ASAT is at maximum and VSAT is at minimum. Finally, the worst value is obtained in the range of the relative window using the relative window and the degradation table already prepared, and the quantitatively determined delay time degradation value can be obtained (FIG. 4C: acquisition of delay degradation value).
A more detailed analysis method in case there are a plurality of adjacent wires is described by the present inventors in: xe2x80x9cMulti-aggressor Relative Window Methodxe2x80x9d; Proceedings of IEEE Custom Integrated Circuits Conference 2000, pp. 495-498 (hereinafter referred as the reference 2).
In the meantime, with the purpose of avoiding and reducing delay time degradation due to crosstalk, it is necessary to achieve such reduction by accurately calculating and evaluating the influence of the signal arrival time as described above. The reference 1 gives an example. Delay gate is inserted to a bus, where the signal arrives earlier when the signal arrival time at the gate output for driving the wire in question has a greater width, and signal arrival time for each bus is equalized. The signal arrival time at the wire in question is narrowed down and is separated from the signal arrival time of the adjacent wire in order to reduce crosstalk. In another example, when signal arrival time of two wires located on adjacent tracks is closer to each other, one of the wires is replaced with the wire on the other track, and signal arrival time is separated in order to reduce crosstalk. JP-A-11-40677 (hereinafter referred as the reference 3) describes a method to insert delay gate and to eliminate crosstalk error when there is timing overlap in signal arrival time.
As described above, when a circuit is realized within narrow space, wires are arranged at positions closer to each other, and there arises a problem that delay time is degraded due to crosstalk. Delay time degradation due to crosstalk does not necessarily occur at all times, and it occurs when the wire in question is changed at a timing closer to the adjacent wire in terms of time. However, signal arrival time of each of the wire in question and the adjacent wire is dynamically changed in response to the change of the input pattern. By taking this into account, it is desirable to accurately analyze delay time degradation due to crosstalk and to address this problem only when the problem arises.
The designing of LSI can be generally carried out by dividing steps such as logic synthesis, arrangement, and wiring. Specifically, a designer first uses the so-called logic synthesis tool on a logic circuit described in design language and generates an information as to what gate is logically connected and how (the so-called net list). Next, physical position of the gate used is determined (arranged).
Finally, the arranged gates are connected with each other, i.e. wiring is performed. Here, with the purpose of solving the problem of delay time degradation due to crosstalk, an example to insert a delay gate is shown as a method described in the references 1 or 3. In this way, to insert the delay gate means that change occurs in the logic gate used in the circuit. Therefore, among the above three steps, change occurs in the step of logic synthesis. Thus, in association with this, it is necessary to carry out the step of arrangement and the step of wiring again. This re-designing leads to the increase of the work for designing LSI (working period and number of working processes), and this causes serious problem.
In summing up, when it is tried to reduce delay time degradation due to crosstalk based on the fact that signal arrival time of each of the wire in question and the adjacent wire is dynamically changed in response to the changes of the input pattern, it is important to carry out re-designing with less time and labor.
Further, the method as described in the reference 3 is a method to reduce crosstalk when there is timing overlap in the signal arrival time. In this sense, when there is no timing overlap (except the case where the relative signal arrival time is 0 as shown in FIG. 2), delay time degradation due to crosstalk cannot be reduced.
It is an object of the present invention to provide an electronic circuit device with reduced crosstalk and a method for designing such a device.
It is another object of the present invention to provide a method for efficiently designing an electronic circuit system on high-performance integrated circuit or on printed circuit board, with less delay time degradation due to crosstalk even in case where signal arrival time of each of the wire in question and the adjacent wire is dynamically changed according to the input signal pattern.
It is still another object of the present invention to provide a method for designing an electronic logic circuit device in order to the reduce delay time degradation due to crosstalk between the wire in question and the adjacent wire by minimizing the increase of the designing work in case where signal arrival time of each of the wire in question and the adjacent wire is dynamically changed according to the input signal pattern.
The present invention provides a method for designing an electronic circuit device without increasing the designing work in case delay time degradation due to crosstalk is reduced according to the fact that signal arrival time of each of the wire in question and the adjacent wire is dynamically changed in response to the change of the input pattern. For this purpose, according to the present invention, the range of relative signal arrival time (relative window in the reference 1) on the wires adjacent to each other (victim and aggressor) is calculated. Then, delay degradation amount is calculated according to the positional relationship, and if the degradation amount does not meet the design constraint and causes a problem, the degradation amount is reduced.
The principle of the reduction of crosstalk common to all features of the present invention is based on the method as shown in FIG. 5 to FIG. 7. FIG. 5 to FIG. 7 each represents how the degradation is reduced using a graph of delay time degradation value with relative signal arrival time RSAT represented on axis of abscissa.
In FIG. 5, in the case before the action is taken (upper portion in the table), the relative window in delay time degradation curve touches a portion, which is not 0, and degradation occurs (DD in the figure). In contrast, when signal arrival time window of aggressor is delayed by a certain means (lower portion of the table), relative window in the delay time degradation curve does not touch a portion, which is not 0, and the delay time degradation value is turned to 0.
Next, in FIG. 6, in the case before the action is taken (upper portion of the table), the relative window in the delay time degradation curve touches a portion, which is not 0, and degradation occurs (DD in the figure). In contrast, if the delay time degradation curve is reduced in size using a certain means (lower portion of the table), the relative window in the delay time degradation curve does not touch a portion, which is not 0, and the delay time degradation value is turned to 0.
Further, in FIG. 7, in the case before the action is taken (upper portion of the table), the relative window in the delay time degradation curve touches a portion, which is not 0, and degradation occurs (DD in the figure). In contrast, if the aggressor can be replaced with the one different from the case before the action is taken using a certain means (i.e. the one adjacent to v is changed from a1 to a2) (lower portion of the table), the relative window is changed, and it does not touch a portion, which is not 0, in the delay time degradation curve, and the delay time degradation value is turned to 0.
In each of the examples shown in FIG. 5 to FIG. 7, description has been given on the case where delay time degradation value is completely turned to 0 by the action taken. However, it is needless to say that, if the reduction meets the design constraint, it will suffice even when the delay time degradation value is not completely turned to 0.
With the purpose of reducing delay time degradation as described above without increasing the designing work, this is accomplished by using a logic gate comprising a transistor with different threshold voltage (the so-called Vth).
This is shown in FIGS. 8A to 8C. First, in FIG. 8A, it is supposed that a certain design constraint relating to delay time is applied on a path from a node A to a node B and on a path from a node C to a node D. In the figure, a wire 801 is adjacent to a wire 802, and crosstalk occurs on this portion. In case delay time is calculated on the assumption that there is no crosstalk, even if design constraint is met on the path from the node A to the node B, violation of the design constraint takes place on this portion because there is degradation of delay time due to crosstalk. Regarding to the path from the node C to the node D, it is assumed that there is some flexibility in the design constraint of the delay time. FIG. 8B and FIG. 8C each represents a situation where the circuit of FIG. 8A is physically arranged on the chip and is connected. These are schematical plan views of an LSI chip and cells arranged in the chip respectively as seen from above the chip. That is, FIG. 8B shows an image of the chip, and FIG. 8C represents cells in the chip. In FIG. 8A, wires 801 and 802 where crosstalk occurs correspond to 803 and 804 in FIG. 8B and to 805 and 806 in FIG. 8C. It is now tried to reduce the crosstalk in accordance with the principle shown in FIG. 5 using gates with different threshold values (the so-called Vth). It is assumed that the window of signal arrival time of the wire 805 corresponds to xe2x80x9caxe2x80x9d (aggressor) in FIG. 5, and that the window of signal arrival time of the wire 806 corresponds to xe2x80x9cvxe2x80x9d (victim) in FIG. 5. A logic gate g4 is a gate to drive the aggressor xe2x80x9caxe2x80x9d in FIG. 5, and this gate is designed with a transistor having threshold value higher than the threshold value as initially in use. Normally, a logic gate comprising a transistor having higher threshold value has longer delay time than a logic gate comprising a transistor having lower threshold value. Therefore, the signal arrival time at the aggressor xe2x80x9caxe2x80x9d is delayed. As a result, the relationship between the relative window and the delay degradation amount is changed as shown in FIG. 5, and the problem is solved. The transistors with different threshold values can be achieved by changing ion injection amount using a mask or by changing potential on the semiconductor substrate on this portion. In any of these cases, it is possible to change the threshold value with respect to the designed data as achieved through the steps of logic synthesis, arrangement and wiring, and there is no need to repeat the steps of logic synthesis, arrangement and wiring. As a result, it is possible to reduce the crosstalk without increasing the designing work.
Further, according to the present invention, delay time degradation can be reduced by combining wires with different vertical/lateral connecting ratio in either of capacitance or inductance of the wires. This is shown in FIGS. 9A to 9D. FIG. 9A represents a circuit diagram similar to that of FIG. 8A, and it is also assumed that the conditions such as design constraint relating to delay time are the same. A wire 901 and a wire 902 where crosstalk occurs are turned to a wire 903 and a wire 904 in FIG. 9B with logic gates connected with each other on the cells similarly to FIG. 8C. FIG. 9C shows an enlarged view of these wires, and the wires 903 and 904 correspond to wires 905 and 906 respectively. FIGS. 9B and 9C each represents a schematical plan view of cells and wire tracks arranged on the chip as seen from above the chip. Normally, when wiring is performed using a design tool, it is laid out in such manner that wires are placed on wire tracks disposed with a certain width and spacing. Therefore, the wires 905 and 906 are shown as wires with the same width on adjacent track in the figure. Here, it is assumed that the window of signal arrival time of the wire 905 corresponds to xe2x80x9cvxe2x80x9d in FIG. 6 and the window of signal arrival time of the wire 906 corresponds to xe2x80x9caxe2x80x9d in FIG. 6. In case wire tracks with wires with different widths are provided partially, it is possible to reduce delay time degradation due to crosstalk. This is shown in FIG. 9D. Here, it is assumed that, in the step of wiring at first, the wires 901 and 902 in FIG. 9A are arranged on the wire track of the same width adjacent to each other as shown by the wires 907 and 908. In this step, delay time analysis using relative window is performed, and it is found that these wires cause delay time degradation due to crosstalk and this violates the design constraint. In such case, if the wire 901 is laid out using a wire 909 on a wire track with wider width (instead of the wire 907), it is possible to reduce the crosstalk. This is because, if the victim can be achieved using a wire with wider width, the capacitance of the wire itself is high, and this leads to higher connecting ratio in either of capacitance in vertical direction (i.e. a direction toward depth in a laminated wire layer), and the connecting ratio of capacitance in lateral direction with respect to the adjacent wire is decreased. As a result, the delay time degradation curve in FIG. 6 can be reduced in size. In this case, too, there is no need to change the arrangement of logic gates as in the case where threshold value is changed, and this means that designing work is not increased. The wiring is to be changed, and this can be accomplished by changing from FIG. 10A to FIG. 10B in the plan view of the wire pattern. Therefore, the problem can be addressed by mere local change, i.e. the change of connecting point of vertical wire and lateral wire in the figure without changing the wire track of lateral wire. For this reason, there is less influence on the other wires, and this also contributes to the prevention of the increase of designing work.
Further, according to the present invention, wiring is carried out with due consideration on the characteristics of window of signal arrival time, and this makes it possible to reduce delay time degradation. This is shown in FIGS. 11A to 11D. In the design steps such as logic synthesis, arrangement and wiring, if arrangement is made without taking adjacent relationship of victim and aggressor into account, it would be turned to the status as shown in FIG. 11A. Here, it is arranged in such manner that nets with wide window of signal arrival time and nets with narrow window are locally concentrated and brought together. That is, in regions 1101 and 1103, there are extremely many nets with wide window. In regions 1102 and 1104, there are extremely many nets with narrow window. In such case, it would be difficult to replace the aggressor by changing the wire tracks as shown in FIGS. 10A and 10B. Specifically, a wire track is shown in FIG. 11B, giving enlarged views of regions 1101 and 1103. As shown on the right portion of FIG. 11B, there are only the nets with wide window, and no matter how the wire tracks are allocated, the relationship between relative window and delay degradation amount is turned to unfavorable condition. Now, description will be given on a method to avoid such situation referring to FIG. 11C. This figure is a view of a chip and wire tracks in each region as seen from above and shows that signal arrival time windows of the wire nets arranged there are narrow or wide. According to the method of the present invention, instead of the arrangement as shown in the left portion of FIG. 11C, it is arranged in such manner that nets with wide windows and nets with narrow windows are approximately in equal numbers as shown in the right portion of FIG. 11C (i.e. the nets with wide windows and the nets with narrow windows are present at less than a given ratio in each space). As a result, the wires can be allocated to have favorable condition as shown in the right portion of FIG. 11D. Even when delay time degradation due to crosstalk may occur in a net 2 and a net 3 with wire allotment as shown in the left portion of FIG. 11D, if the net 3 is replaced with a net 5, the relationship between relative window and delay degradation amount can be improved in the right portion of FIG. 11D similarly to the case shown in FIG. 7. In this case, too, there is no need to change the logic gates or to insert delay gate, and crosstalk can be reduced without increasing the designing work.
Further, according to the present invention, delay time degradation can be reduced by allocating wire track to be used by wire nets according to the characteristics of window of signal arrival time. This is shown in FIGS. 12A and 12B. FIG. 12A shows signal arrival time window of the wire nets. In case of a net 1, signal arrival time window is positioned in the first half in the cycle time (e.g. cycle CT of clock signal). In case of a net 2, signal arrival time window is positioned in the second half in the cycle time. Here, these nets are classified into two classes, and class 1 is allocated as window in the first half and class 2 is allocated as window in the second half. When these wire nets are allocated on wire tracks as shown in FIG. 12B, only the wire of class 1 is arranged on an odd-numbered wire track, and only the wire of class 2 is arranged on an even-numbered wire track. Then, the relationship between relative window and delay degradation amount of the wire nets allocated on adjacent wire tracks (on odd-numbered wire track and even-numbered wire track) will be turned to favorable condition. That is, it is not the status as xe2x80x9cvxe2x80x9d and xe2x80x9ca1xe2x80x9d in FIG. 7, but it is turned to the status as xe2x80x9cvxe2x80x9d and xe2x80x9ca2xe2x80x9d, and delay time degradation due to crosstalk is reduced. In this case, too, there is no influence on synthesis step and arrangement step, and it would suffice only to consider locally on the allocation of wire tracks in the wiring step. Thus, there is no need to increase the designing work.
As it is evident from the above description, a wide variety of inventions are disclosed in the present application. These can be summarized as follows:
Specifically, the first invention of the present application provides a method for designing an electronic circuit device, comprising the steps of calculating a possible range of relative signal arrival time from ranges of dynamic signal arrival time in each of a wire in question and a wire adjacent thereto, and calculating delay time degradation between the wire in question and the adjacent wire using an information on delay time degradation due to crosstalk retrievable by the relative signal arrival time, whereby logic gates for driving each of the wire in question or the adjacent wire and at least a part of logic gates located closer to input side than the above logic gates comprise transistor having threshold value different from threshold value of transistor of the other logic gates with the purpose of reducing delay time degradation due to crosstalk as calculated.
The second invention of the present application provides an electronic circuit device to reduce delay time degradation due to crosstalk by arranging in such manner that logic gates for driving each of the wire in question and the wire adjacent thereto and at least a part of logic gates located closer to input side than the above logic gates comprise transistor having threshold value different from threshold value of transistor of the other logic gates.
The third invention of the present application provides a method for designing an electronic circuit device, and the method comprises the steps of calculating a possible range of relative signal arrival time from ranges of dynamic signal arrival time at each of a wire in question and a wire adjacent thereto, calculating delay time degradation between the wire in question and the wire adjacent thereto using an information on delay time degradation due to crosstalk retrievable by the relative signal arrival time, and arranging at least one of the wire in question or the adjacent wire on a wire track having connecting ratio in either of capacitance or inductance of vertical wire layer to lateral wire layer with the purpose of reducing delay time degradation due to crosstalk as calculated.
The fourth invention of the present application provides a method for designing an electronic circuit device, comprising the steps of calculating a range of dynamic signal arrival time in wire nets, each serving input/output of logic gates, when a plurality of logic gates are arranged in distributed plural sections in a plurality of spaces, classifying the ranges of signal arrival time to wire nets and narrow nets based on a given reference, and arranging the logic gates in such manner that wire net ratio for each class of the ranges of signal arrival time will be less than a given ratio in each space, and further performing wiring with the purpose of reducing delay time degradation due to crosstalk.
The fifth invention of the present application provides a method for designing an electronic circuit device, comprising the steps of calculating ranges of dynamic signal arrival time in wire nets, each serving as input/output of logic gates, classifying the ranges of signal arrival time into a plurality of classes as early-arriving nets and delayed-arriving nets, and arranging a net of the class designated in advance among the classes to each wire track of the wire nets for the purpose of reducing delay time degradation due to crosstalk.
The sixth invention of the present application provides an electronic logic circuit device, comprising wire nets classified into a plurality of classes of early-arriving nets and delayed-arriving nets using the range of signal arrival time as a reference, and also comprising a plurality of wire track of the wire nets, whereby the net of the class designated in advance is arranged on the wire track for the purpose of reducing delay time degradation due to crosstalk.
The seventh invention of the present application provides a method for designing an electronic circuit device, comprising the steps of calculating possible range of relative signal arrival time from range of dynamic signal arrival time of each of a wire in question and a wire adjacent thereto in the circuit when designing a semiconductor chip comprising a plurality of signal paths connecting a plurality of electronic circuit blocks incorporated therein or designing an electronic circuit device where the semiconductor chip is provided on a circuit substrate and an electronic circuit is formed, calculating delay time degradation between the wire in question and the adjacent wire using information on delay time degradation due to crosstalk retrievable by the relative signal arrival time, and placing a delay element arranged in distributed manner in advance in the semiconductor chip, a delay element intensively arranged around a circuit block in the semiconductor chip, or a delay element intensively arranged around the semiconductor chip on the substrate to signal paths including the wire in question or the adjacent wire with the purpose of reducing delay time degradation due to crosstalk as calculated.
The eighth invention of the present application provides an electronic logic circuit device, wherein there are provided a first wire layer comprising an electronic logic circuit having relatively lower delay time degradation value and a second wire layer comprising an electronic logic circuit having relatively higher delay time degradation value than the first wire layer, the two wire layers being laminated on a single substrate, a third wire layer being disposed via a first inter-layer insulating film with relatively smaller thickness above or below the second wire layer, and a fourth wire layer being disposed via a second inter-layer insulating film with relatively greater thickness above or below the first wire layer.